US 12,256,542 B2
Three-dimensional memory device containing a pillar contact between channel and source and methods of making the same
Kyohei Nabesaka, Yokkaichi (JP); and Teruo Okina, Yokkaichi (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Sep. 12, 2022, as Appl. No. 17/931,362.
Application 17/931,362 is a continuation in part of application No. 17/684,975, filed on Mar. 2, 2022, granted, now 12,108,597.
Prior Publication US 2024/0090217 A1, Mar. 14, 2024
Int. Cl. H10B 41/27 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/20 (2023.02) [H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure that comprises a memory die, wherein the memory die comprises:
an alternating stack of insulating layers and electrically conductive layers;
a semiconductor material layer located over the alternating stack;
a dielectric spacer layer located over the semiconductor material layer, and spaced from the alternating stack by the semiconductor material layer;
a memory opening vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer;
a memory opening fill structure located in the memory opening and comprising a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, a memory film; and
a source layer located over the dielectric spacer layer and contacting the pillar portion of the vertical semiconductor channel.