US 12,256,541 B2
Apparatus and method including memory device having 2-transistor vertical memory cell
Durai Vishak Nirmal Ramaswamy, Boise, ID (US); and Kamal M. Karda, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 29, 2021, as Appl. No. 17/515,024.
Prior Publication US 2023/0132576 A1, May 4, 2023
Int. Cl. H10B 41/35 (2023.01); H01L 21/02 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/788 (2006.01)
CPC H10B 41/35 (2023.02) [H01L 21/02565 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/78642 (2013.01); H01L 29/7869 (2013.01); H01L 29/7889 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory cell including:
a first transistor including a first channel region, and a charge storage structure separated from the first channel region;
a second transistor including a second channel region formed over the charge storage structure, wherein a direction from the second channel region to the charge storage structure is a first direction; and
a dielectric structure formed in a trench, the dielectric structure including a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench, wherein the charge storage structure is between and adjacent the first and second dielectric portions;
an additional dielectric material different from the second dielectric portion and contacting the second dielectric portion, wherein the second dielectric portion is between the charge storage structure and the additional dielectric material, and a direction from the charge storage structure to the additional dielectric material is a second direction perpendicular to the first direction.