US 12,256,540 B2
Three-dimensional memory devices with improved back-side channel structures
Kun Zhang, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Zhiliang Xia, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jun. 18, 2021, as Appl. No. 17/352,239.
Application 17/352,239 is a continuation of application No. PCT/CN2021/081997, filed on Mar. 22, 2021.
Prior Publication US 2022/0302149 A1, Sep. 22, 2022
Int. Cl. H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a stack structure comprising interleaved conductive layers and dielectric layers;
a plurality of channel structures extending through the stack structure, each channel structure comprising a memory film and a semiconductor channel, wherein the semiconductor channel comprises a doped portion, and a part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction;
a filling layer in contact with a top dielectric layer of the stack structure and having a first thickness; and
a doped semiconductor layer comprising:
a lateral portion of the doped semiconductor layer covering the filling layer, and
a plurality of protruding portions of the doped semiconductor layer each extending vertically from the lateral portion of the doped semiconductor layer, and encasing an end of the part of the doped portion of the semiconductor channel of a corresponding channel structure
an interlayer dielectric layer covering the doped semiconductor layer; and
a redistribution layer comprising:
a lateral portion of the redistribution layer covering the interlayer dielectric layer,
a first protruding portion of the redistribution layer extending vertically from a first side of the lateral portion of the redistribution layer and in contact with the doped semiconductor layer; and
a first recess on a second side of the lateral portion of the redistribution layer and aligned with the first protruding portion of the redistribution layer in a vertical direction.