| CPC H10B 20/25 (2023.02) [H01L 23/5256 (2013.01)] | 18 Claims |
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1. A memory device, comprising:
a plurality of memory cells, each one of which includes a first transistor, a second transistor, and a resistor operatively coupled to each other in series;
wherein the first transistor includes a first sub-transistor having:
a first channel structure;
a first source structure disposed on one side of the first channel structure; and
a first drain structure disposed on the other side of the first channel structure;
wherein the second transistor includes a second sub-transistor having:
a second channel structure;
a second source structure disposed on one side of the second channel structure; and
a second drain structure disposed on the other side of the second channel structure;
wherein the resistor includes a first metal structure, a second metal structure, and a third metal structure,
wherein the first metal structure is disposed above the first and second transistors and electrically coupled to the first drain structure,
wherein the second metal structure is disposed above the first and second transistors and electrically coupled to the second source structure,
wherein the third metal structure is disposed above the first and second metal structures and electrically coupled to the first drain structure through the first metal structure,
wherein the third metal structure is configured to be burned down upon the first and second transistors being activated; and
wherein the first channel structure, the first source structure, the first drain structure, the second channel structure, the second source structure, and the second drain structure are all formed in a first active region of a substrate.
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