US 12,256,538 B2
Anti-fuse unit structure and anti-fuse array
Xiong Li, Hefei (CN); and Peng Feng, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Appl. No. 17/310,859
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
PCT Filed Mar. 18, 2021, PCT No. PCT/CN2021/081498
§ 371(c)(1), (2) Date Aug. 26, 2021,
PCT Pub. No. WO2021/203937, PCT Pub. Date Oct. 14, 2021.
Claims priority of application No. 202010264022.4 (CN), filed on Apr. 7, 2020.
Prior Publication US 2022/0320121 A1, Oct. 6, 2022
Int. Cl. H10B 20/20 (2023.01); H10B 20/25 (2023.01)
CPC H10B 20/25 (2023.02) 17 Claims
OG exemplary drawing
 
1. An anti-fuse unit structure, comprising:
a substrate;
an anti-fuse device, formed in the substrate, comprising a first gate structure, a first source doped region, and a first drain doped region, wherein the first gate structure is electrically connected to the first drain doped region; and
a select transistor, formed in the substrate and matched with the anti-fuse device, comprising a second gate structure, a second source doped region and a second drain doped region, wherein the second drain doped region is electrically connected to the first source doped region;
wherein the first gate structure comprises a first gate dielectric layer and a first gate conductive layer, the first gate conductive layer is made of a metal composite layer; and
wherein the metal composite layer has three layers, an upper layer is made of metal tungsten, a middle layer is made of titanium nitride, and a lower layer is made of polysilicon.