US 12,256,536 B2
Semiconductor base plate and semiconductor device
Qiang Long, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on May 11, 2022, as Appl. No. 17/662,891.
Application 17/662,891 is a continuation of application No. PCT/CN2021/125530, filed on Oct. 22, 2021.
Claims priority of application No. 202111020690.3 (CN), filed on Sep. 1, 2021.
Prior Publication US 2023/0064989 A1, Mar. 2, 2023
Int. Cl. H10B 20/20 (2023.01); H10B 20/25 (2023.01)
CPC H10B 20/20 (2023.02) [H10B 20/25 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A semiconductor base plate, comprising:
a semiconductor substrate, comprising an array region and a peripheral region, wherein
the array region comprises a primary memory cell;
the peripheral region comprises an antifuse memory cell and secondary memory capacitors, one of the secondary memory capacitors is electrically connected to the antifuse memory cell;
the peripheral region further comprises a repair control circuit, the repair control circuit is connected to the antifuse memory cell, and the repair control circuit is connected to the secondary memory capacitor by using the antifuse memory cell, and when it is determined that a primary memory cell in the array region is damaged, the repair control circuit is configured to control a corresponding antifuse memory cell to operate, to replace the damaged primary memory cell with the secondary memory capacitor connected electrically; and
the antifuse memory cell and the primary memory cell formed by a same process.