	US 12,256,535 B2
	Semiconductor device and method for forming semiconductor device
Sheng Li, Hefei (CN); and Xing Jin, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 8, 2021, as Appl. No. 17/520,786.
Application 17/520,786 is a continuation of application No. PCT/CN2021/113623, filed on Aug. 19, 2021.
Claims priority of application No. 202110524592.7 (CN), filed on May 13, 2021.
Prior Publication US 2022/0367477 A1, Nov. 17, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01)

CPC H10B 12/482 (2023.02) [H01L 21/32139 (2013.01); H01L 21/76811 (2013.01); H01L 21/7682 (2013.01); H01L 21/76877 (2013.01)]

7 Claims

1. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate, the semiconductor substrate comprising a plurality of bit line structures disposed at intervals along a first direction;

a surface of each of the plurality of bit line structures is filled with a conductive material to form a conductive layer, wherein a top surface of the conductive layer is higher than a top surface of each of the plurality of bit line structures; and

etching the conductive layer to form a plurality of first conductive layers independent of each other and a plurality of second conductive layers, each of which is located on a respective one of the first conductive layers;

wherein the conductive material comprises a first conductive material and a second conductive material; the conductive layer comprises a first initial conductive layer and a second initial conductive layer;

the surface of each of the plurality of bit line structures is filled with the conductive material to form the conductive layer, comprises:

the surface of each of the plurality of bit line structures is filled with the first conductive material to form the first initial conductive layer;

etching back the first initial conductive layer to expose a portion of each of the plurality of bit line structures; and

filling a surface of the first initial conductive layer after being etched back with the second conductive material to form the second initial conductive layer, wherein a top surface of the second initial conductive layer is higher than a top surface of each of the plurality of bit line structures; and,

wherein each of the bit line structures comprises a bit line contact layer, a bit line metal layer and a bit line mask layer that are sequentially stacked along a third direction, the third direction is perpendicular to a plane where the semiconductor substrate is located; and

etching back the first initial conductive layer to expose a portion of each of the plurality of bit line structures, comprises:

etching back the first initial conductive layer to expose the bit line mask layer;

filling the surface of the first initial conductive layer after being etched back with the second conductive material to form the second initial conductive layer, wherein the top surface of the second initial conductive layer is higher than a top surface of the bit line mask layer,

wherein etching the conductive layer to form the plurality of the first conductive layers independent of each other and the plurality of the second conductive layers, each of which is located on a respective one of the plurality of first conductive layers, comprises:

sequentially performing, along the third direction, a first etching treatment on the first initial conductive layer and the second initial conductive layer, to form first etching conductive layers independent of each other along a second direction and second etching conductive layers independent of each other along the second direction; and

performing, along the third direction, a second etching treatment on the second etching conductive layers, to form the plurality of first conductive layers independent of each other and the plurality of second conductive layers, each of which is located on the respective one of the first conductive layers,

wherein the second direction is perpendicular to the first direction, a plane formed by the second direction and the first direction is parallel to a plane where the semiconductor substrate is located,

the first etching treatment comprises:

forming a first mask layer with a first mask pattern on the top surface of the second initial conductive layer; and

sequentially etching, through the first mask layer, the second initial conductive layer and the first initial conductive layer to make both the second initial conductive layer and the first initial conductive layer have the first mask pattern, so as to form the first etching conductive layers independent of each other along the second direction and the second etching conductive layers independent of each other along the second direction,

wherein the first mask layer comprises a first hard mask layer, a first anti-reflective layer and a first photoresist layer that are stacked in sequence;

forming the first mask layer having the first mask pattern on the top surface of the second initial conductive layer comprises:

forming the first hard mask layer, the first anti-reflective layer and the first photoresist layer on the top surface of the second initial conductive layer, wherein the first photoresist layer has a first initial mask pattern;

forming an isolation layer on surfaces of the first photoresist layer having the first initial mask pattern;

sequentially etching the isolation layer and the first initial mask pattern with a part of the isolation layer located on side walls of the first initial mask pattern retained, to form an isolation side wall pattern; and

etching, through the isolation side wall pattern, the first anti-reflective layer and the first hard mask layer to form the first mask layer having the first mask pattern.