US 12,256,534 B2
Semiconductor device having double bit capacity and method for manufacturing the same
Ying-Chieh Lai, Zhubei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jul. 5, 2023, as Appl. No. 18/218,218.
Application 18/218,218 is a division of application No. 17/866,720, filed on Jul. 18, 2022.
Prior Publication US 2024/0023313 A1, Jan. 18, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/34 (2023.02) [H10B 12/053 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate comprising:
a first active region having a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region; and
an isolation layer adjacent to the first active region;
a trench in the semiconductor substrate intersecting the first sub-active region and the second sub-active region of the first active region;
a word line structure in the trench and adjacent to the first active region, wherein the word line structure comprises:
a word line insulating layer covering inner side surfaces of the trench;
a word line electrode on the word line insulating layer; and
a word line capping structure on the word line electrode,
wherein a depth of the first separation channel is substantially identical to a thickness of the isolation layer;
wherein a thickness of the word line structure is substantially identical to a thickness of the isolation layer.