US 12,256,533 B2
Semiconductor memory device and method of fabricating the same
Ken-Li Chen, Quanzhou (CN); Yifei Yan, Quanzhou (CN); and Yu-Cheng Tung, Quanzhou (CN)
Assigned to Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Jan. 31, 2024, as Appl. No. 18/427,852.
Application 18/427,852 is a continuation of application No. 17/573,597, filed on Jan. 11, 2022, granted, now 11,930,631.
Claims priority of application No. 202111327962.4 (CN), filed on Nov. 10, 2021; and application No. 202122747174.2 (CN), filed on Nov. 10, 2021.
Prior Publication US 2024/0244824 A1, Jul. 18, 2024
Int. Cl. H10B 12/00 (2023.01); H10D 62/10 (2025.01)
CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/482 (2023.02); H10D 62/115 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate;
a plurality of bit lines separately disposed on the substrate;
a plurality of plugs disposed on the substrate, the plugs and the bit lines being alternately arranged with each other;
a spacer structure, disposed on the substrate between each of the bit lines and each of the plugs;
a plurality of storage node pads disposed on the plugs and the bit lines, wherein the storage node pads respectively contact the plugs;
a plurality of capacitors disposed on the storage node pads to respectively in alignment with the storage node pads, each of the capacitors comprising a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked sequentially, wherein a bottommost surface of the capacitor dielectric layer is lower than a topmost surface of the storage node pads; and
an insulating layer disposed on the bit lines, the plugs and the spacer structure, wherein each of the bit lines comprises a semiconductor layer, a barrier layer and a metal layer stacked sequentially, and the insulating layer directly contacts the metal layer.