US 12,256,530 B2
Method of manufacturing semiconductor structure, semiconductor structure and memory
Kui Zhang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on May 18, 2022, as Appl. No. 17/663,871.
Claims priority of application No. 202111314977.7 (CN), filed on Nov. 8, 2021.
Prior Publication US 2023/0147028 A1, May 11, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/0387 (2023.02) [H10B 12/312 (2023.02); H10B 12/482 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a first semiconductor layer on the substrate, wherein the first semiconductor layer comprises a first trench region and a to-be-doped region on two opposite sides of the first trench region, and the first trench region and the to-be-doped region are arranged in a direction parallel to a surface of the substrate;
forming a word line, wherein the word line surrounds a sidewall surface of a part of the first semiconductor layer in the first trench region, and at least a part of a projection of a part of the first semiconductor layer in the to-be-doped region on the surface of the substrate coincides with a projection of the word line on the surface of the substrate;
forming a doping body portion, wherein the doping body portion comprises first dopant ions, and the doping body portion contacts an end surface of the to-be-doped region away from the first trench region; and
performing an annealing, such that the first dopant ions diffuse to the to-be-doped region, the to-be-doped region is converted into a doped region, and along a direction that the doped region points to the first trench region, a concentration of dopant ions in the doped region is decreased progressively.