US 12,256,496 B2
Electronic device including interposer
Jungsik Park, Suwon-si (KR); and Soyoung Lee, Gwacheon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 6, 2023, as Appl. No. 18/502,657.
Application 18/502,657 is a continuation of application No. 17/971,146, filed on Oct. 21, 2022, granted, now 11,818,843.
Application 17/971,146 is a continuation of application No. 17/185,283, filed on Feb. 25, 2021, granted, now 11,483,930, issued on Oct. 25, 2022.
Application 17/185,283 is a continuation of application No. 16/887,585, filed on May 29, 2020, granted, now 10,939,552, issued on Mar. 2, 2021.
Application 16/887,585 is a continuation of application No. 16/121,085, filed on Sep. 4, 2018, granted, now 10,674,607, issued on Jun. 2, 2020.
Claims priority of application No. 10-2017-0116517 (KR), filed on Sep. 12, 2017.
Prior Publication US 2024/0074059 A1, Feb. 29, 2024
Int. Cl. H05K 1/14 (2006.01); G06F 1/16 (2006.01); G06F 1/20 (2006.01); G06F 1/26 (2006.01); H01Q 1/52 (2006.01); H01Q 9/04 (2006.01); H01R 12/53 (2011.01); H04B 1/3883 (2015.01); H04M 1/02 (2006.01); H05K 1/11 (2006.01); H01Q 1/24 (2006.01); H01Q 9/42 (2006.01); H01Q 21/06 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01)
CPC H05K 1/144 (2013.01) [G06F 1/1626 (2013.01); G06F 1/1635 (2013.01); G06F 1/1656 (2013.01); G06F 1/1658 (2013.01); G06F 1/1698 (2013.01); G06F 1/203 (2013.01); G06F 1/263 (2013.01); H01Q 1/526 (2013.01); H01Q 9/0407 (2013.01); H01R 12/53 (2013.01); H04B 1/3883 (2013.01); H04M 1/026 (2013.01); H04M 1/0262 (2013.01); H04M 1/0277 (2013.01); H05K 1/116 (2013.01); H01Q 1/243 (2013.01); H01Q 9/42 (2013.01); H01Q 21/065 (2013.01); H05K 1/0216 (2013.01); H05K 1/147 (2013.01); H05K 1/181 (2013.01); H05K 2201/042 (2013.01); H05K 2201/10037 (2013.01); H05K 2201/10098 (2013.01); H05K 2201/10189 (2013.01); H05K 2201/10371 (2013.01); H05K 2201/10378 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a first circuit board;
a second circuit board; and
an interposer including a first surface and a second surface connected with the first circuit board and the second circuit board, respectively,
wherein an inner space is formed by the first circuit board, the second circuit board and a side wall of the interposer between the first surface and the second surface,
wherein a lateral outer surface of the side wall facing a first direction perpendicular to a direction in which the first circuit board and the second circuit board face comprises a first plating region, a second plating region, and a non-plating region located between the first plating region and the second plating region,
wherein an inner lateral surface of the side wall facing a second direction opposite to the first direction and perpendicular to the direction in which the first circuit board and the second circuit board face comprises a third plating region, and
wherein a substantially entire length of the non-plating region is overlapped with the third plating region when viewed from a direction substantially perpendicular to the lateral outer surface.