US 12,256,487 B2
Hybrid boards with embedded planes
Jackson Chung Peng Kong, Tanjung Tokong (MY); Bok Eng Cheah, Gelugor (MY); Jenny Shio Yin Ong, Bayan Lepas (MY); Seok Ling Lim, Kulim (MY); Chin Lee Kuan, Pahang (MY); and Tin Poay Chuah, Bayan Baru (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 6, 2021, as Appl. No. 17/367,674.
Prior Publication US 2021/0410273 A1, Dec. 30, 2021
Int. Cl. H05K 1/02 (2006.01); H05K 3/46 (2006.01)
CPC H05K 1/0218 (2013.01) [H05K 3/4688 (2013.01); H05K 2201/0187 (2013.01); H05K 2201/093 (2013.01); H05K 2201/09536 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A interconnect stack comprising:
a first dielectric layer with a first dielectric constant and a first dielectric loss tangent;
an intermediate layer comprising:
a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent;
an embedded conductive layer;
a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, wherein the embedded conductive layer is positioned between the first and second dielectric sublayers; and
a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, wherein the intermediate layer is positioned between the first and second dielectric layers;
wherein the first dielectric layer, first dielectric sublayer, second dielectric layer, and the second dielectric sublayer have different dielectric constants and dielectric loss tangents to form a hybrid structure.