| CPC H04W 72/23 (2023.01) [H04L 1/1812 (2013.01); H04W 92/18 (2013.01)] | 26 Claims |

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1. An apparatus, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the apparatus to:
receive, at a first user equipment (UE) and from a second UE, both an indication of sidelink resources for reception of a sidelink shared channel transmission from the second UE and an indication of uplink resources for providing sidelink feedback information associated with the sidelink shared channel transmission to a network device;
monitor, at the first UE, the indicated sidelink resources for the sidelink shared channel transmission;
generate, at the first UE, the sidelink feedback information associated with the sidelink shared channel transmission in accordance with the monitoring;
obtain, at the first UE and based on generating the sidelink feedback information, a state of a sidelink communication link between the first UE and the second UE, the state indicating that the sidelink communication link is blocked; and
transmit, from the first UE and based on the state of the sidelink communication link indicating that the sidelink communication link is blocked, the sidelink feedback information associated with the sidelink shared channel transmission to the network device via an uplink communication link between the first UE and the network device using the indicated uplink resources, wherein the sidelink feedback information indicates whether the sidelink shared channel transmission is decoded by the first UE.
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