US 12,255,984 B2
Data invalidation for memory
Daniele Vimercati, El Dorado Hills, CA (US); and Simon J. Lovett, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 26, 2021, as Appl. No. 17/331,578.
Prior Publication US 2022/0385451 A1, Dec. 1, 2022
Int. Cl. H04L 9/06 (2006.01); G06F 3/06 (2006.01); G06F 21/62 (2013.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G06F 7/58 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/0643 (2013.01) [G06F 3/0623 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 21/6245 (2013.01); G11C 29/38 (2013.01); G11C 29/4401 (2013.01); G06F 7/588 (2013.01); G06F 21/62 (2013.01); H04L 9/08 (2013.01); H04L 9/0869 (2013.01); H04L 2209/08 (2013.01); H04L 2209/12 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method, comprising:
generating, after a first event, a first set of scrambling sequences for a plurality of addresses received in association with a first plurality of commands for accessing the plurality of addresses of a memory array;
accessing, in response to the first plurality of commands, portions of the memory array based at least in part on the first set of scrambling sequences, the portions of the memory array corresponding to the plurality of addresses and comprising scrambled first data, the scrambled first data comprising first data scrambled with the first set of scrambling sequences;
generating, after a subsequent event, a second set of scrambling sequences for the plurality of addresses as received in association with a second plurality of commands for accessing the plurality of addresses after the subsequent event, the second set of scrambling sequences being different than the first set of scrambling sequences, wherein the scrambled first data stored in the portions of the memory array is rendered invalid as a result of the scrambled first data including the first set of scrambling sequences and as a result of the second set of scrambling sequences being generated; and
accessing, in response to the second plurality of commands associated with second data, the portions of the memory array after the scrambled first data stored in the portions of the memory array are rendered invalid as the result of the scrambled first data including the first set of scrambling sequences and as a result of the second set of scrambling sequences being generated, wherein the portions of the memory array comprise the second data scrambled with the second set of scrambling sequences.