| CPC H04L 7/00 (2013.01) [H03L 7/0807 (2013.01); G01R 31/31727 (2013.01); G01R 31/31919 (2013.01)] | 20 Claims |
|
1. A controller, comprising:
a first interface to a clock recovery unit that provides a recovered clock from the first interface to the clock recovery unit;
a memory that stores instructions; and
a processor that executes the instructions, wherein, when executed by the processor, the instructions cause the controller to:
instruct, via the first interface, the clock recovery unit at a first loop bandwidth to provide the recovered clock to a signal sampler to measure a signal from a device under test;
instruct, via the first interface, the clock recovery unit at a second loop bandwidth wider than the first loop bandwidth to provide the recovered clock to the signal sampler to measure the signal from the device under test;
compare measurements from the signal sampler at the first loop bandwidth to measurements from the signal sampler at the second loop bandwidth; and
instruct, via the first interface, the clock recovery unit at a third loop bandwidth to provide the recovered clock to the signal sampler applying adjustments based on comparing the measurements from the signal sampler at the first loop bandwidth to measurements from the signal sampler at the second loop bandwidth.
|