US 12,255,759 B2
Time-variable decision feedback equalization
Timothy M. Hollis, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Sep. 26, 2023, as Appl. No. 18/373,122.
Application 18/373,122 is a continuation of application No. 17/874,939, filed on Jul. 27, 2022, granted, now 11,777,767.
Application 17/874,939 is a continuation of application No. 17/149,364, filed on Jan. 14, 2021, granted, now 11,418,370, issued on Aug. 16, 2022.
Prior Publication US 2024/0022457 A1, Jan. 18, 2024
Int. Cl. H04L 25/03 (2006.01)
CPC H04L 25/03057 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, at a decision feedback equalization (DFE) circuit of a dynamic random access memory (DRAM) device, an input signal via a Data In or Out (DQ) line of the DRAM device, wherein the DFE circuit comprises a delay circuit including a plurality of delay elements;
configuring, by the delay circuit, the plurality of delay elements to have one of a first configuration of the plurality of delay elements or a second configuration of the plurality of delay elements;
generating, by the delay circuit, after receiving the input signal, one or more delay signals resulting from the input signal in accordance with the one of the first configuration of the plurality of delay elements or the second configuration of the plurality of delay elements that is configured for the plurality of delay elements; and
generating, by a variable gain circuit that comprises a plurality of amplifiers, one or more amplified delay signals in accordance with a first configuration of the plurality of amplifiers, wherein a feedback signal generated by the variable gain circuit comprises the one or more amplified delay signals.