US 12,255,729 B2
Integrated mixed-signal ASIC with ADC, DAC, and DSP
Paul Rutt, Longmont, CO (US); Erik Buehler, Castle Rock, CO (US); and Damon Van Buren, Parker, CO (US)
Assigned to Seakr Engineering, LLC, Centennial, CO (US)
Filed by Seakr Engineering, LLC, Centennial, CO (US)
Filed on May 25, 2023, as Appl. No. 18/201,821.
Application 18/201,821 is a continuation of application No. 17/668,177, filed on Feb. 9, 2022, granted, now 11,711,139.
Application 17/668,177 is a continuation of application No. 17/142,778, filed on Jan. 6, 2021, granted, now 11,329,718, issued on May 10, 2022.
Application 17/142,778 is a continuation of application No. 16/286,567, filed on Feb. 26, 2019, granted, now 10,917,163, issued on Feb. 9, 2021.
Application 16/286,567 is a continuation in part of application No. 15/351,224, filed on Nov. 14, 2016, granted, now 10,218,430, issued on Feb. 26, 2019.
Application 16/286,567 is a continuation in part of application No. 15/263,134, filed on Sep. 12, 2016, granted, now 10,243,650, issued on Mar. 26, 2019.
Application 15/351,224 is a continuation of application No. 14/828,126, filed on Aug. 17, 2015, granted, now 9,461,732, issued on Oct. 4, 2016.
Application 15/263,134 is a continuation of application No. 14/828,126, filed on Aug. 17, 2015, granted, now 9,461,732, issued on Oct. 4, 2016.
Claims priority of provisional application 62/037,816, filed on Aug. 15, 2014.
Prior Publication US 2024/0146402 A1, May 2, 2024
Int. Cl. H04B 7/185 (2006.01); H04B 1/00 (2006.01); H04B 1/40 (2015.01)
CPC H04B 7/18515 (2013.01) [H04B 1/0039 (2013.01); H04B 1/40 (2013.01); H04B 7/1851 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An integrated analog to digital converting and digital to analog converting (ADDA) radio frequency (RF) transceiver for satellite applications, the RF transceiver being contained on one or more die, all located on the same package, the RF transceiver comprising:
a plurality of high speed analog to digital conversion (ADC) units, each configured for conversion of an analog RF input signal to a sampled digital signal;
a plurality of high speed digital to analog conversion (DAC) units, each configured for conversion of processed digital data to an analog RF output signal;
a plurality of digital inputs;
a plurality of digital outputs;
one or more first digital signal processing (DSP) cores configured to process data from a high speed ADC unit of the plurality of high speed ADC units and output the processed data to a digital output of the plurality of digital outputs; and
one or more second digital signal processing (DSP) cores configured to process data from a digital input of the plurality of digital inputs and output the processed data to a high speed DAC unit of the plurality of high speed DAC units;
wherein the RF transceiver is configured to mitigate Single Event Effect (SEE) induced events with a duration less than 1 nanosecond (ns).