US 12,255,666 B2
Generalized LDPC encoder, generalized LDPC encoding method and storage device
Daeyeol Yang, Suwon-si (KR); Bohwan Jun, Suwon-si (KR); Hongrak Son, Suwon-si (KR); Geunyeong Yu, Suwon-si (KR); and Youngjun Hwang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 24, 2023, as Appl. No. 18/225,313.
Claims priority of application No. 10-2022-0127935 (KR), filed on Oct. 6, 2022.
Prior Publication US 2024/0120945 A1, Apr. 11, 2024
Int. Cl. H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/13 (2006.01); H03M 13/15 (2006.01); H03M 13/19 (2006.01)
CPC H03M 13/116 (2013.01) [H03M 13/1102 (2013.01); H03M 13/1108 (2013.01); H03M 13/1111 (2013.01); H03M 13/1137 (2013.01); H03M 13/1174 (2013.01); H03M 13/1177 (2013.01); H03M 13/611 (2013.01); H03M 13/616 (2013.01); H03M 13/6561 (2013.01); H03M 13/6563 (2013.01); H03M 13/13 (2013.01); H03M 13/152 (2013.01); H03M 13/19 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A generalized low-density parity-check (G-LDPC) encoder comprising:
a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure comprising information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders comprises a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and
an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder comprises a plurality of single check nodes configured to perform a single parity check,
wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and
wherein the LDPC encoder is configured to:
obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders,
determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and
output the information bits, the inner parity bits, and the outer parity bits as a codeword.