US 12,255,660 B2
Independently clocking digital loop filter by time-to-digital converter in digital phase-locked loop
Avri Harush, Herzeliya (IL)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Jun. 12, 2023, as Appl. No. 18/333,452.
Application 18/333,452 is a continuation of application No. 17/704,578, filed on Mar. 25, 2022, granted, now 11,677,404.
Prior Publication US 2024/0007113 A1, Jan. 4, 2024
Int. Cl. H03L 7/093 (2006.01); G04F 10/00 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/093 (2013.01) [G04F 10/005 (2013.01); H03L 7/0991 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A time-to-digital converter (TDC) circuit comprising:
phase error calculation circuitry to determine phase error values based on an input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit; and
clock generation circuitry to:
generate a filter clock that asserts a clock pulse in response to detecting each last received pulse of the input reference clock and the feedback clock; and
provide the filter clock to a digital loop filter (DLF) concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.