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1. A clock monitor circuit, comprising a plurality of delay cells, each delay cell including a delay portion coupled to a comparator portion, the delay portions connected in series to form a delay line, the delay line configured to generate an array of delayed clock signals from a monitored clock signal, each comparator portion configured to perform a comparison which compares a delayed clock signal to an expected value for at least one of: a monitored clock signal period, a monitored clock signal high time duration, or a monitored clock signal low time duration, each comparator portion also configured to output a failure detection signal indicating whether the expected values are met.
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