US 12,255,654 B2
Slew rate acceleration circuit and buffer circuit including the same
Dukmin Lee, Seoul (KR); and Kyeongwoo Kim, Siheung-si (KR)
Assigned to Magnachip Mixed-Signal, Ltd., Cheongju-si (KR)
Filed by Magnachip Mixed-Signal, Ltd., Cheongju-si (KR)
Filed on Oct. 8, 2021, as Appl. No. 17/497,000.
Claims priority of application No. 10-2021-0036348 (KR), filed on Mar. 22, 2021.
Prior Publication US 2022/0302910 A1, Sep. 22, 2022
Int. Cl. H03K 5/02 (2006.01); H03F 3/45 (2006.01)
CPC H03K 5/02 (2013.01) [H03F 3/45475 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A slew rate acceleration circuit in a buffer circuit, the slew rate acceleration circuit being configured to:
detect, via a current detection circuit, a current flowing through a load stage of the buffer circuit, the load stage comprising a current mirror circuit;
compare, via a control circuit, a value of the detected current with an adjustable reference value; and
supply, via the control circuit, an adjusting driving voltage to an output stage comprising at least one driving transistor of the buffer circuit based on results of the comparison for increasing a slew rate of the buffer circuit,
wherein the slew rate acceleration circuit comprises a first bias transistor and a second bias transistor, and is configured to adjust the adjustable reference value according to a first bias voltage applied to a gate electrode of the first bias transistor and a second bias voltage applied to a gate electrode of the second bias transistor,
wherein the control circuit comprises at least one acceleration transistor, and a source electrode of the at least one acceleration transistor is connected to a gate electrode of the at least one driving transistor, and
wherein the slew rate acceleration circuit is further configured to detect the current flowing through the load stage based on a gate voltage of a transistor constituting the current mirror circuit.