US 12,255,653 B2
Methods and devices for digital clock multiplication of a clock to generate a high frequency output
Ali Azam, Hillsboro, OR (US); Ashoke Ravi, Portland, OR (US); and Benjamin Jann, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/356,564.
Prior Publication US 2022/0416770 A1, Dec. 29, 2022
Int. Cl. H03K 5/00 (2006.01); G06F 7/68 (2006.01); H03K 5/02 (2006.01)
CPC H03K 5/00006 (2013.01) [G06F 7/68 (2013.01); H03K 5/02 (2013.01); H03K 2005/00286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital clock multiplier (DCM) circuit comprising:
a plurality of phase shift generators, each configured to:
receive a respective driving clock phase of a plurality of driving clock phases; and
generate a plurality of phase shifts based on the respective driving clock phase, wherein in the plurality of phase shift generators are delay lock loops (DLLs) or digitally controlled edge-interpolators (DCEIs);
a plurality of power amplifier (PA) rows, wherein each of the plurality of phase shift generators is coupled to a respective one of the plurality of PA rows,
wherein each PA row comprises a plurality of cascade switched capacitor power amplifier (SCPA) unit cells arranged into groups, each group of cascade SCPA unit cells configured to:
receive one phase shift of the plurality of phase shifts based on the respective driving clock phase; and
one or more processors configured to:
disable one or more cascade SCPA unit cells of each group based on the plurality of phase shifts;
generate an output signal for each group of the plurality of cascade SCPA unit cells; and
combine the output signal of each group of the plurality of cascade SCPA unit cells to generate a PA row output signal.