US 12,255,650 B2
Operational amplifier-based hysteresis comparator and chip
Yutian Chen, Shenzhen (CN); and Lvfan Yi, Shenzhen (CN)
Assigned to SHENZHEN GOODIX TECHNOLOGY CO., LTD, Shenzhen (CN)
Filed by SHENZHEN GOODIX TECHNOLOGY CO., LTD., Shenzhen (CN)
Filed on May 26, 2023, as Appl. No. 18/324,661.
Claims priority of application No. 202211099992.9 (CN), filed on Sep. 9, 2022.
Prior Publication US 2024/0088874 A1, Mar. 14, 2024
Int. Cl. H03K 3/02 (2006.01); G01R 19/165 (2006.01); H03F 1/34 (2006.01); H03F 3/45 (2006.01); H03K 3/0233 (2006.01); H03K 5/22 (2006.01); H03K 5/24 (2006.01)
CPC H03K 3/02337 (2013.01) [G01R 19/16504 (2013.01); G01R 19/16566 (2013.01); H03F 1/342 (2013.01); H03F 3/45264 (2013.01); H03F 3/45273 (2013.01); H03K 5/22 (2013.01); H03K 5/2481 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An operational amplifier-based hysteresis comparator, configured to compare a first voltage with a second voltage, the hysteresis comparator comprising: an input stage and an amplification stage connected with the input stage, wherein
the input stage comprises: a first input branch and a second input branch, wherein the first input branch generates a first current based on the first voltage, and the second input branch generates a second current based on the second voltage,
the first input branch comprises N number of connected input sub-branches, N is determined based on a first selection signal, and when Nis greater than or equal to 2, N input sub-branches are connected in parallel,
the second input branch comprises M number of connected input sub-branches, M is determined based on a second selection signal, and when M is greater than or equal to 2, M input sub-branches are connected in parallel,
M and N are positive integers, and at least one of M and N is greater than or equal to 2, and
the amplification stage comprises: a first input terminal, a second input terminal, and an output terminal, the first current is connected with the first input terminal, the second current is connected with the second input terminal, the output terminal outputs a first level when the first current is greater than the second current, the output terminal outputs a second level when the first current is less than the second current, the first level is a high level, and the second level is a low level;
wherein when N is a positive integer greater than 2, and the first input branch comprises N−1 number of first input sub-branches and one second input sub-branch, a width-to-length ratio of each first input transistor in the N−1 number of first input sub-branches is different; and
when M is a positive integer greater than 2, and the second input branch comprises M−1 number of fourth input sub-branches and one third input sub-branch, a width-to-length ratio of each fourth input transistor in the M−1 number of fourth input sub-branches is different.