US 12,255,644 B2
Audio interface physical layer
Atul Kumar Agrawal, Bangalore (IN); Abhijit Patki, Bangalore (IN); and Shaik Basha, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 28, 2022, as Appl. No. 18/058,988.
Prior Publication US 2024/0178838 A1, May 30, 2024
Int. Cl. H03K 19/00 (2006.01); G06F 3/16 (2006.01); H03K 5/01 (2006.01); H03K 19/21 (2006.01); H04R 3/00 (2006.01); H04R 3/12 (2006.01); H03K 5/00 (2006.01)
CPC H03K 19/0002 (2013.01) [G06F 3/162 (2013.01); H03K 5/01 (2013.01); H03K 19/21 (2013.01); H04R 3/005 (2013.01); H04R 3/12 (2013.01); H03K 2005/00013 (2013.01); H04R 2430/01 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
an input buffer having a buffer output;
a first delay circuit having a first delay circuit input and a first delay circuit output, the first delay circuit input coupled to the buffer output;
a second delay circuit having a second delay circuit input and a second delay circuit output, the second delay circuit input coupled to the first delay circuit output;
a first logic gate having a first logic gate input, a second logic gate input, and a first logic gate output, the first logic gate input coupled to the first delay circuit output, and the second logic gate input coupled to the second delay circuit output;
a second logic gate having a third logic gate input, a fourth logic gate input, and a second logic gate output, the third logic gate input coupled to the first logic gate output; and
a tristatable output buffer having a control input, the control input coupled to the second logic gate output.