| CPC H03H 17/0671 (2013.01) [H03H 17/0664 (2013.01); H03H 2017/0678 (2013.01)] | 19 Claims |
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1. A device for processing interleaved signals, comprising:
an integrator configured to receive an interleaved signal and output an integrated interleaved signal, wherein the interleaved signal comprises a plurality of digital signals interleaved at an input clock rate;
a downsampler coupled to the integrator to receive the integrated interleaved signal and buffer a portion of each of the digital signals of the integrated interleaved signal; and
a comb filter coupled to the downsampler to receive the portions of the digital signal and to output a decimated interleaved signal corresponding to the portions of the digital signals interleaved at clock rate corresponding the input clock rate divided by a decimation rate, wherein the downsampler comprises a first-in first-out (FIFO) buffer, and wherein a number of storage elements of the FIFO buffer corresponds to the number of the plurality of digital signals, and wherein the portions of each of the digital signals are based on the decimation rate.
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