US 12,255,594 B2
Amplifier with a converting circuit with reduced intrinsic time constant
Luca Piazzon, Segrate (IT)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Dec. 23, 2021, as Appl. No. 17/561,053.
Application 17/561,053 is a continuation of application No. PCT/EP2019/066772, filed on Jun. 25, 2019.
Prior Publication US 2022/0116003 A1, Apr. 14, 2022
Int. Cl. H03F 3/45 (2006.01); H03F 3/00 (2006.01); H03K 19/09 (2006.01); H03K 19/17784 (2020.01)
CPC H03F 3/45497 (2013.01) [H03F 3/005 (2013.01); H03K 19/09 (2013.01); H03K 19/17784 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An amplifier, comprising:
a converting circuit configured to convert a differential input signal into a single ended output signal, the converting circuit comprising:
an input section configured to receive the differential input signal; and
an output section comprising an output port configured to provide the single ended output signal, wherein the output section comprises a capacitive element configured to reduce an intrinsic time constant of the converting circuit, wherein a capacitance of the capacitive element is larger than an output parasitic capacitance of the input section.