US 12,255,588 B2
Cascode amplifier bias circuits
Jonathan James Klaren, San Diego, CA (US); David Kovac, Arlington Heights, IL (US); Eric S. Shapiro, San Diego, CA (US); Christopher C. Murphy, Lake Zurich, IL (US); Robert Mark Englekirk, Littleton, CO (US); Keith Bargroff, San Diego, CA (US); and Tero Tapio Ranta, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Apr. 2, 2024, as Appl. No. 18/624,973.
Application 17/843,372 is a division of application No. 16/935,999, filed on Jul. 22, 2020, granted, now 11,374,540, issued on Jun. 28, 2022.
Application 16/935,999 is a division of application No. 16/250,889, filed on Jan. 17, 2019, granted, now 10,756,678, issued on Aug. 25, 2020.
Application 16/250,889 is a division of application No. 15/268,229, filed on Sep. 16, 2016, granted, now 10,250,199, issued on Apr. 2, 2019.
Application 18/624,973 is a continuation of application No. 18/322,166, filed on May 23, 2023, granted, now 11,955,932.
Application 18/322,166 is a continuation of application No. 17/843,372, filed on Jun. 17, 2022, granted, now 11,664,769, issued on May 30, 2023.
Prior Publication US 2024/0348211 A1, Oct. 17, 2024
Int. Cl. H03F 1/22 (2006.01); H03F 1/30 (2006.01); H03F 1/56 (2006.01); H03F 3/193 (2006.01); H03F 3/195 (2006.01); H03F 3/213 (2006.01); H03F 3/24 (2006.01)
CPC H03F 1/223 (2013.01) [H03F 1/301 (2013.01); H03F 1/56 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H03F 3/245 (2013.01); H03F 2200/102 (2013.01); H03F 2200/105 (2013.01); H03F 2200/165 (2013.01); H03F 2200/18 (2013.01); H03F 2200/21 (2013.01); H03F 2200/222 (2013.01); H03F 2200/225 (2013.01); H03F 2200/243 (2013.01); H03F 2200/294 (2013.01); H03F 2200/297 (2013.01); H03F 2200/301 (2013.01); H03F 2200/306 (2013.01); H03F 2200/387 (2013.01); H03F 2200/391 (2013.01); H03F 2200/399 (2013.01); H03F 2200/42 (2013.01); H03F 2200/451 (2013.01); H03F 2200/48 (2013.01); H03F 2200/489 (2013.01); H03F 2200/492 (2013.01); H03F 2200/498 (2013.01); H03F 2200/555 (2013.01); H03F 2200/61 (2013.01); H03F 2200/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected transistor stages, each transistor stage having a gate, a drain, and a source, the bottom transistor stage having an input configured to be coupled to an RF input signal to be amplified, and the top transistor stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a cascode reference circuit having at least two serially connected transistor stages, each transistor having a gate, a drain, and a source, the gates of the bottom two transistor stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two transistor stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;
(c) coupling a first current source to the drain of the top transistor stage of the cascode reference circuit;
(d) providing a voltage offset circuit including a resistor series-connected between a first current source and a second current source, the drain of the top transistor stage of the cascode reference circuit being coupled between the resistor and the first current source; and
(e) providing a source follower transistor having a gate, a drain, and a source, the drain of the source follower transistor being coupled to a voltage source, the source of the source follower transistor being coupled to a third current source and to the respective gates of the bottom transistor stages of the cascode reference circuit and the cascode amplifier, and the gate of the source follower transistor being coupled to the voltage offset circuit between the resistor and the second current source, the source follower transistor being responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom transistor stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value.