US 12,255,587 B2
Gate drivers for stacked transistor amplifiers
Poojan Wagh, Sleepy Hollow, IL (US); Kashish Pal, Reading (GB); Robert Mark Englekirk, Littleton, CO (US); Tero Tapio Ranta, San Diego, CA (US); Keith Bargroff, San Diego, CA (US); and Simon Edward Willard, Irvine, CA (US)
Assigned to PSEMI CORPORATION, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Aug. 9, 2023, as Appl. No. 18/447,207.
Application 15/690,115 is a division of application No. 15/268,275, filed on Sep. 16, 2016, granted, now 9,843,293, issued on Dec. 12, 2017.
Application 18/447,207 is a continuation of application No. 17/531,510, filed on Nov. 19, 2021, granted, now 11,742,802.
Application 17/531,510 is a continuation of application No. 16/882,061, filed on May 22, 2020, granted, now 11,190,139, issued on Nov. 30, 2021.
Application 16/882,061 is a continuation of application No. 16/240,601, filed on Jan. 4, 2019, granted, now 10,700,642, issued on Jun. 30, 2020.
Application 16/240,601 is a continuation of application No. 15/690,115, filed on Aug. 29, 2017, granted, now 10,389,306, issued on Aug. 20, 2019.
Prior Publication US 2024/0039479 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 1/22 (2006.01); H03F 1/02 (2006.01); H03F 3/193 (2006.01)
CPC H03F 1/0211 (2013.01) [H03F 1/0261 (2013.01); H03F 1/223 (2013.01); H03F 3/193 (2013.01); H03F 2200/18 (2013.01); H03F 2200/21 (2013.01); H03F 2200/451 (2013.01); H03F 2200/522 (2013.01)] 18 Claims
OG exemplary drawing
 
10. A circuital arrangement comprising:
a transistor stack configured to operate as an amplifier, the transistor stack comprising an input transistor and one or more cascode transistors; and
a biasing circuit coupled to one or more gates of the one or more cascode transistors, the biasing circuit comprising:
a first resistive ladder network comprising one or more high impedance nodes; and
a second resistive ladder network comprising one or more low impedance nodes; wherein
during a first mode of operation of the circuital arrangement, the one or more high impedance nodes are coupled to the one or more gates to provide respective biasing voltages, and
during the second mode of operation, the one or more low impedance nodes are coupled to the one or more gates to provide respective biasing voltages and wherein a current through the second resistive ladder network during the second mode of operation is substantially larger than a current through the first resistive ladder network during the first mode of operation.