US 12,255,585 B2
Qubit control electronics
Joseph Cheney Bardin, Amherst, MA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Feb. 6, 2024, as Appl. No. 18/434,726.
Application 18/434,726 is a division of application No. 17/251,370, granted, now 11,929,711, previously published as PCT/US2019/018584, filed on Feb. 19, 2019.
Claims priority of provisional application 62/729,316, filed on Sep. 10, 2018.
Prior Publication US 2024/0429866 A1, Dec. 26, 2024
Int. Cl. H03D 7/00 (2006.01); B82Y 10/00 (2011.01); G06F 1/20 (2006.01); G06N 10/00 (2022.01); H01F 6/00 (2006.01); H02M 1/08 (2006.01); H03D 7/14 (2006.01); H03K 3/38 (2006.01); H03K 17/693 (2006.01); H03K 17/92 (2006.01); H03K 19/195 (2006.01); H03M 1/12 (2006.01); H04B 10/077 (2013.01); H04B 10/70 (2013.01)
CPC H03D 7/005 (2013.01) [B82Y 10/00 (2013.01); G06F 1/20 (2013.01); G06N 10/00 (2019.01); H03D 7/1458 (2013.01); H01F 6/00 (2013.01); H02M 1/08 (2013.01); H03K 3/38 (2013.01); H03K 17/693 (2013.01); H03K 17/92 (2013.01); H03K 19/195 (2013.01); H03M 1/12 (2013.01); H04B 10/077 (2013.01); H04B 10/70 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A quantum computing system comprising:
a cooling device capable of providing a plurality of cooling stages, wherein each cooling stage is maintained at a different temperature;
a qubit chip comprising a qubit, wherein the qubit chip is arranged in the cooling device and maintained at a first cooling stage, wherein a temperature of the first cooling stage is between 0 K and 100 mK; and
a control circuit for generating a qubit XY control signal arranged in the cooling device and maintained at a second cooling stage, wherein a temperature of the second cooling stage is above the temperature of the first cooling stage and below room temperature, and wherein the control circuit is coupled to qubit chip.