US 12,255,256 B2
Transistor structure with metal interconnection directly connecting gate and drain/source regions
Chao-Chun Lu, Taipei (TW)
Assigned to Etron Technology, Inc., Hsinchu (TW); and Invention And Collaboration Laboratory Pte. Ltd., Singapore (SG)
Filed by Etron Technology, Inc., Hsinchu (TW); and Invention And Collaboration Laboratory Pte. Ltd., Singapore (SG)
Filed on Oct. 5, 2023, as Appl. No. 18/376,839.
Application 18/376,839 is a continuation of application No. 17/468,683, filed on Sep. 8, 2021, granted, now 11,855,218.
Claims priority of provisional application 63/075,841, filed on Sep. 9, 2020.
Prior Publication US 2024/0030347 A1, Jan. 25, 2024
Int. Cl. H01L 29/76 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01)
CPC H01L 29/7851 (2013.01) [H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/1033 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A transistor structure comprising:
a semiconductor substrate with a semiconductor surface;
a gate structure above the semiconductor surface, and a first concave formed to reveal the gate structure;
a channel region under the semiconductor surface; and
a first conductive region electrically coupled to the channel region, and a second concave formed to reveal the first conductive region;
wherein a mask pattern in a photolithography process is used to define the first concave, the mask pattern only defines one dimension length of the first concave, and a shape of the mask pattern is different from a shape of the first concave.