| CPC H01L 29/7805 (2013.01) [H01L 29/1608 (2013.01); H01L 29/7811 (2013.01)] | 14 Claims |
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1. A semiconductor device, comprising:
an element region including a transistor and a first diode;
a termination region surrounding the element region and including a second diode; and
an intermediate region provided between the element region and the termination region,
wherein the element region includes:
a first electrode;
a second electrode;
a gate electrode;
a silicon carbide layer provided between the first electrode and the second electrode, having a first face on a side of the first electrode and a second face on a side of the second electrode, and including:
a first silicon carbide region of a first conductive type including a first region and a second region, the first region being in contact with the first face and facing the gate electrode, and the second region being in contact with the first face and in contact with the first electrode;
a second silicon carbide region of a second conductive type provided between the first silicon carbide region and the first face, the second silicon carbide region being adjacent to the first region, the second silicon carbide region facing the gate electrode, and the second silicon carbide region electrically connected to the first electrode; and
a third silicon carbide region of a first conductive type provided between the second silicon carbide region and the first face and electrically connected to the first electrode; and
a gate insulating layer provided between the gate electrode and the second silicon carbide region and between the gate electrode and the first region,
the termination region includes:
a first wiring layer electrically connected to the first electrode, the first wiring layer including a first portion, a second portion, a third portion, and a fourth portion, the first portion extending in a second direction perpendicular to a first direction parallel to the first face, the second direction being parallel to the first face, the second portion extending in the second direction, the third portion extending in the first direction, the fourth portion extending in the first direction, the first electrode being interposed between the first portion and the second portion and between the third portion and the fourth portion;
the second electrode; and
the silicon carbide layer including the first silicon carbide region and a fourth silicon carbide region of a second conductive type, the first silicon carbide region including a third region, the third region being in contact with the first face and in contact with the first wiring layer, the fourth silicon carbide region provided between the first silicon carbide region and the first face and electrically connected to the first wiring layer, and
the intermediate region includes:
a gate electrode pad;
a second wiring layer electrically connected to the gate electrode pad and the gate electrode and including a first line and a second line, the first line extending in the second direction and provided between the first portion and the first electrode, and the second line extending in the second direction and provided between the second portion and the first electrode;
the second electrode;
a first connection layer electrically connecting the first electrode and the fourth portion to each other; and
a second connection layer electrically connecting the first electrode and the third portion to each other,
wherein the intermediate region further includes a gate wiring layer provided between the second connection layer and the silicon carbide layer, the gate wiring layer electrically connected to the gate electrode pad and the first line.
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