US 12,255,251 B2
Semiconductor device including first gate electrode and second gate electrode
Roman Baburske, Otterfing (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jun. 22, 2023, as Appl. No. 18/212,906.
Application 18/212,906 is a continuation of application No. 17/402,516, filed on Aug. 14, 2021, granted, now 11,728,417.
Claims priority of application No. 102020121771.4 (DE), filed on Aug. 19, 2020.
Prior Publication US 2023/0343863 A1, Oct. 26, 2023
Int. Cl. H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/7397 (2013.01) [H01L 29/0696 (2013.01); H01L 29/1095 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a drift region of a first conductivity type in a semiconductor body having a first main surface;
a body region of a second conductivity type between the drift region and the first main surface; and
a plurality of trenches extending into the semiconductor body from the first main surface and patterning the semiconductor body into a plurality of mesas,
wherein the plurality of trenches includes:
a first trench having an electrode electrically coupled to a first gate driver output;
a second trench having an electrode electrically coupled to the first gate driver output;
a third trench having an electrode electrically coupled to a second gate driver output;
a fourth trench having an electrode electrically coupled to a first load contact terminal; and
a fifth trench having an electrode electrically coupled to the first load contact terminal,
wherein the third trench, the fourth trench, and the fifth trench are arranged between the first trench and the second trench,
wherein a width of a channel configured to be controlled by the gate electrode in the first trench differs from a width of a channel configured to be controlled by the both electrode in the second trench and the electrode in the third trench.