	US 12,255,249 B2
	Inner spacer structures for gate-all-around field effect transistors
Mrunal Abhijith Khaderbad, Hsinchu (TW); Keng-Chu Lin, Ping-Tung (TW); and Yu-Yun Peng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,674.
Application 18/446,674 is a continuation of application No. 17/818,786, filed on Aug. 10, 2022, granted, now 11,804,539.
Application 17/818,786 is a continuation of application No. 17/075,863, filed on Oct. 21, 2020, granted, now 11,488,869, issued on Nov. 1, 2022.
Prior Publication US 2023/0387254 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01)

CPC H01L 29/66553 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/4991 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 21/0234 (2013.01)]

20 Claims

1. A structure, comprising:

a plurality of nanostructure layers on a substrate;

a source/drain (S/D) structure on the substrate and adjacent to the plurality of nanostructure layers;

a gate structure surrounding the plurality of nanostructure layers; and

a spacer structure interposed between the gate structure and the S/D structure, wherein the spacer structure comprises:

a seam in the spacer structure and separated from a concave side surface of the spacer structure, wherein the concave side surface is between the seam and the S/D structure.