| CPC H01L 29/66545 (2013.01) [H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 23/5286 (2013.01); H01L 27/088 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01)] | 9 Claims |

|
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a bottleneck-shaped backside contact structure in a semiconductor device, the backside contact structure having two sides in a substrate and partially within a first source/drain structure of the semiconductor device, wherein the semiconductor device has one or more source/drain structures, one or more channel structures and wherein the substrate is on a first side of the semiconductor device;
wherein the forming the bottleneck-shaped backside contact structure is performed such that the bottleneck-shaped backside contact structure includes:
a first side partially within the first source/drain structure and a second side opposite to the first side;
a first portion having a first slope that has a positive slope and a second portion, adjacent to the first portion, the second portion having a second slope that has a greater slope value than the first slope; and
the first portion and the second portion include: a liner extending from the first side to the second side, wherein the liner includes a first region comprised of either a Ta silicide liner or a Ti silicide liner, a second region comprised of a Ti or TiN liner and a third region comprised of either a Ta silicide liner or a Ti silicide liner.
|