US 12,255,247 B2
Trench contact structures for advanced integrated circuit structure fabrication
Subhash M. Joshi, Hillsboro, OR (US); Jeffrey S. Leib, Beaverton, OR (US); and Michael L. Hattendorf, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 18, 2024, as Appl. No. 18/416,508.
Application 18/416,508 is a continuation of application No. 18/135,624, filed on Apr. 17, 2023, granted, now 11,948,997.
Application 18/135,624 is a continuation of application No. 17/243,476, filed on Apr. 28, 2021, granted, now 11,664,439, issued on May 30, 2023.
Application 17/243,476 is a continuation of application No. 16/509,395, filed on Jul. 11, 2019, granted, now 11,088,261, issued on Aug. 10, 2021.
Application 16/509,395 is a continuation of application No. 15/859,410, filed on Dec. 30, 2017, granted, now 10,957,782, issued on Mar. 23, 2021.
Claims priority of provisional application 62/593,149, filed on Nov. 30, 2017.
Prior Publication US 2024/0162332 A1, May 16, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/167 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01); H10B 10/00 (2023.01); H01L 23/00 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/0337 (2013.01); H01L 21/28247 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 21/3086 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/76232 (2013.01); H01L 21/76801 (2013.01); H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/5329 (2013.01); H01L 27/0207 (2013.01); H01L 27/0886 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 28/20 (2013.01); H01L 28/24 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/167 (2013.01); H01L 29/41783 (2013.01); H01L 29/41791 (2013.01); H01L 29/516 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/7843 (2013.01); H01L 29/7845 (2013.01); H01L 29/7846 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 29/7854 (2013.01); H10B 10/12 (2023.02); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/0332 (2013.01); H01L 21/76883 (2013.01); H01L 21/76885 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 29/665 (2013.01); H01L 29/7842 (2013.01); H01L 29/7853 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a fin comprising a semiconductor material, the fin having a channel region;
a gate electrode over the channel region of the fin, the gate electrode having a first side and a second side opposite the first side;
first and second semiconductor source or drain regions adjacent the first and second sides of the gate electrode, respectively;
a trench contact structure over one of the first or second semiconductor source or drain regions, the trench contact structure comprising a T-shaped metal layer on a U-shaped metal layer, the U-shaped metal layer having a lateral width;
a dielectric material between the gate electrode and the trench contact structure, the dielectric material having an uppermost surface; and
an insulating cap layer over the T-shaped metal layer of the trench contact structure, the insulating cap layer having a lateral width greater than a lateral width of the U-shaped metal layer.