US 12,255,244 B2
Field effect transistor including gate insulating layer formed of two-dimensional material
Minhyun Lee, Suwon-si (KR); Minsu Seol, Suwon-si (KR); Ho Won Jang, Seoul (KR); Yeonchoo Cho, Suwon-si (KR); and Hyeonjin Shin, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd, Gyeonggi-do (KR); and SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, Seoul (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR); and SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, Seoul (KR)
Filed on Feb. 20, 2023, as Appl. No. 18/171,502.
Application 18/171,502 is a continuation of application No. 17/060,696, filed on Oct. 1, 2020, granted, now 11,588,034.
Claims priority of application No. 10-2020-0009396 (KR), filed on Jan. 23, 2020.
Prior Publication US 2023/0197811 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/423 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/42364 (2013.01) [H01L 29/045 (2013.01); H01L 29/0665 (2013.01); H01L 29/1606 (2013.01); H01L 29/66439 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A field effect transistor comprising:
a channel layer;
a gate insulating layer including an insulative, high-k, two-dimensional material on the channel layer;
a gate electrode on the gate insulating layer;
a first electrode electrically connected to the channel layer; and
a second electrode electrically connected to the channel layer,
wherein the channel layer comprises a semiconductor material having a two-dimensional crystal structure,
wherein the gate insulating layer comprises a ferroelectric material having a two-dimensional crystal structure,
wherein an interface charge density between the channel layer and the gate insulating layer is 1×1012 per cm2 or less,
wherein the field effect transistor has a subthreshold swing value of about 60 mV/dec or less.