US 12,255,241 B2
Low-k feature formation processes and structures formed thereby
Wan-Yi Kao, Baoshan Township (TW); and Chung-Chi Ko, Nantou (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 18, 2023, as Appl. No. 18/302,434.
Application 18/302,434 is a continuation of application No. 17/222,303, filed on Apr. 5, 2021, granted, now 11,640,978.
Application 17/222,303 is a continuation of application No. 16/715,899, filed on Dec. 16, 2019, granted, now 10,971,589, issued on Apr. 6, 2021.
Application 16/715,899 is a continuation of application No. 15/994,561, filed on May 31, 2018, granted, now 10,510,852, issued on Dec. 17, 2019.
Claims priority of provisional application 62/591,316, filed on Nov. 28, 2017.
Prior Publication US 2023/0275136 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/41791 (2013.01) [H01L 21/28194 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823437 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a gate electrode over a semiconductor fin over a substrate; and
a spacer located adjacent to the gate electrode, wherein at least a portion of the spacer has a density of between 1 g/cm3 and 3 g/cm3, a non-zero carbon concentration less than 30 at. % and a non-zero nitrogen concentration of less than 3 at. %.