US 12,255,240 B2
Topology selective and sacrificial silicon nitride layer for generating spacers for a semiconductor device drain
Tzu-Yang Ho, Hsinchu (TW); Tsai-Jung Ho, Xihu Township (TW); Jr-Hung Li, Chupei (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/342,048.
Application 18/342,048 is a continuation of application No. 17/304,214, filed on Jun. 16, 2021, granted, now 11,742,399.
Prior Publication US 2023/0343842 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02274 (2013.01); H01L 21/0228 (2013.01); H01L 21/31111 (2013.01); H01L 29/401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first silicon nitride layer in an opening of a semiconductor device;
forming a second silicon nitride layer on the first silicon nitride layer;
removing the second silicon nitride layer from the first silicon nitride layer formed on sidewalls of the opening of the semiconductor device;
removing, at a bottom of the opening of the semiconductor device, the first silicon nitride layer and the second silicon nitride layer; and
forming a metal drain in the opening of the semiconductor device.