| CPC H01L 29/4175 (2013.01) [H01L 29/0673 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/665 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a transistor, comprising:
a source/drain region, comprising:
a front surface and a back surface opposite to the front surface; and a salicide region on the back surface;
a channel region in contact with the source/drain region and comprising a front surface co-planar with the front surface of the source/drain region; and
a gate structure disposed on the front surface of the channel region; and
a backside contact structure, comprising:
a conductive contact in contact with the salicide region; and
a liner layer surrounding the conductive contact, wherein a horizontal interface between the liner layer and the source/drain region is coplanar with a horizontal interface between the salicide region and the conductive contact.
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11. A semiconductor device, comprising:
a gate-all-around field effect transistor (GAA FET), comprising:
a plurality of nanowires, wherein a nanowire of the plurality of nanowires comprises a front surface;
a gate dielectric layer wrapping around each nanowire of the plurality of nanowires,
wherein the gate dielectric layer is in contact with the front surface of the nanowire;
a gate electrode disposed on the gate dielectric layer and over the front surface of the nanowire; and
a source/drain (S/D) region in contact with the plurality of nanowires and comprising a front surface and a back surface, wherein the front surface of the S/D region is opposite to the back surface and co-planar with the front surface of the nanowire;
a backside interlayer dielectric (ILD) layer;
a backside contact in the backside ILD layer and comprising:
a salicide layer in contact with a first portion of the back surface of the S/D region;
a conductive contact in contact with the salicide layer; and
a liner layer between the conductive contact and the ILD layer, wherein the liner layer is in contact with a second portion of the back surface of the S/D region, wherein a bottom surface of the liner layer is coplanar with a top surface of the salicide layer; and
an S/D contact in contact with the front surface of the S/D region.
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16. A semiconductor device, comprising:
a channel region on a substrate;
a gate structure surrounding the channel region;
a source/drain (S/D) region on the substrate and abutting the channel region;
a salicide region having a horizontal bottom surface coplanar with a bottom surface of the gate structure;
a conductive contact on the horizontal bottom surface of the salicide region; and
a liner layer on a side surface of the conductive contact.
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