US 12,255,236 B2
Self-aligned active regions and passivation layer and methods of making the same
Hung Wei Li, Hsinchu (TW); Mauricio Manfrini, Zhubei (TW); Sai-Hooi Yeong, Zhubei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,541.
Application 18/446,541 is a continuation of application No. 17/227,460, filed on Apr. 12, 2021, granted, now 11,817,485.
Claims priority of provisional application 63/042,579, filed on Jun. 23, 2020.
Prior Publication US 2023/0387224 A1, Nov. 30, 2023
Int. Cl. H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/41733 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 29/401 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
12. A method of making a field effect transistor comprising:
depositing a word line in a trench over a buffer layer;
forming contact via structure;
depositing a metal layer over the contact via structures;
depositing a semiconductor channel layer over the contact via structure, metal layer, and buffer layer;
annealing the metal layer in direct contact with the semiconducting channel layer to form active regions, wherein the active regions are self-aligned to the contact via structures;
depositing a gate dielectric layer over the buffer layer; and
depositing and planarizing an interconnect level dielectric layer over the semiconducting channel layer and the buffer layer.