US 12,255,234 B2
Integrated circuit structures having germanium-based channels
Siddharth Chouksey, Portland, OR (US); Glenn Glass, Portland, OR (US); Anand Murthy, Portland, OR (US); Harold Kennel, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); Tahir Ghani, Portland, OR (US); Ashish Agrawal, Hillsboro, OR (US); and Seung Hoon Sung, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 10, 2024, as Appl. No. 18/409,509.
Application 18/409,509 is a division of application No. 17/869,622, filed on Jul. 20, 2022, granted, now 11,923,421.
Application 17/869,622 is a division of application No. 16/022,510, filed on Jun. 28, 2018, granted, now 11,437,472, issued on Sep. 6, 2022.
Prior Publication US 2024/0145549 A1, May 2, 2024
Int. Cl. H01L 31/072 (2012.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 31/109 (2006.01)
CPC H01L 29/165 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and an upper silicon germanium portion on the intermediate germanium portion, wherein the intermediate germanium portion has a greater atomic concentration of germanium than the upper silicon germanium portion;
forming an isolation structure along sidewalls of the lower silicon portion of the fin;
forming a gate stack over a top of and along sidewalls of the upper silicon germanium portion of the fin and on a top surface of the isolation structure, the gate stack having a first side opposite a second side;
forming a first source or drain structure at the first side of the gate stack; and
forming a second source or drain structure at the second side of the gate stack.