US 12,255,229 B2
ESD protection device with isolation structure layout that minimizes harmonic distortion
Egle Tylaite, Munich (DE); and Joost Adriaan Willemen, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Aug. 17, 2023, as Appl. No. 18/234,992.
Application 18/234,992 is a continuation of application No. 17/536,253, filed on Nov. 29, 2021, granted, now 11,776,996.
Prior Publication US 2023/0395656 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 29/735 (2006.01); H01L 29/74 (2006.01); H01L 29/861 (2006.01); H01L 29/868 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 29/0692 (2013.01); H01L 29/735 (2013.01); H01L 29/7436 (2013.01); H01L 29/8611 (2013.01); H01L 29/868 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An ESD protection device, comprising:
a semiconductor body comprising an upper surface;
a plurality of p-type wells that each extend from the upper surface into the semiconductor body; and
a plurality of n-type wells that each extend from the upper surface into the semiconductor body;
wherein the p-type wells and the n-type wells alternate with one another in a first direction, and
wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.