US 12,255,207 B2
Boundary design for high-voltage integration on HKMG technology
Yi-Huan Chen, Hsin Chu (TW); Chien-Chih Chou, New Taipei (TW); Alexander Kalnitsky, San Francisco, CA (US); Kong-Beng Thei, Pao-Shan Village (TW); Ming Chyi Liu, Hsinchu (TW); Shih-Chung Hsiao, New Taipei (TW); and Jhih-Bin Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 21, 2023, as Appl. No. 18/515,912.
Application 17/867,771 is a division of application No. 16/797,334, filed on Feb. 21, 2020, granted, now 11,410,999, issued on Aug. 9, 2022.
Application 18/515,912 is a continuation of application No. 17/867,771, filed on Jul. 19, 2022, granted, now 11,855,091.
Prior Publication US 2024/0088154 A1, Mar. 14, 2024
Int. Cl. H01L 27/092 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 23/48 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01P 1/15 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/28008 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/517 (2013.01); H01L 23/481 (2013.01); H01P 1/15 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a substrate comprising a low voltage region, a high voltage region, and a boundary region defined between the low voltage region and the high voltage region;
an isolation structure disposed in the boundary region of the substrate;
a first polysilicon component disposed directly on an upper surface of the substrate alongside the isolation structure;
a boundary dielectric layer disposed on the isolation structure;
a second polysilicon component disposed on the boundary dielectric layer;
a first transistor device disposed within the low voltage region, the first transistor device having a first gate electrode disposed over a first gate dielectric layer; and
a second transistor device disposed within the high voltage region, the second transistor device having a second gate electrode disposed over a second gate dielectric layer, the second transistor device configured to operate at an operation voltage greater than that of the first transistor device,
wherein the first gate electrode is disposed above a surface of the substrate, and the second gate electrode extends below the surface of the substrate.