US 12,255,204 B2
Vertical FET replacement gate formation with variable fin pitch
Ruilong Xie, Niskayuna, NY (US); Yao Yao, Albany, NY (US); Andrew M. Greene, Slingerlands, NY (US); and Veeraraghavan S. Basker, Schenectady, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 20, 2021, as Appl. No. 17/479,145.
Prior Publication US 2023/0086960 A1, Mar. 23, 2023
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/823437 (2013.01); H01L 21/823487 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first set of fins and a second set of fins;
a dielectric pillar disposed between the first set of fins and the second set of fins such that the dielectric pillar extends above a topmost surface of the first and second set of fins;
a first bottom source/drain (S/D) region directly contacting a bottom surface of the first set of fins and a second bottom S/D region directly contacting a bottom surface of the second set of fins;
a first top S/D region directly contacting a top surface of the first set of fins and a second top S/D region directly contacting a top surface of the second set of fins, wherein sidewalls of the first and second top S/D regions directly contact sidewalls of the dielectric pillar, wherein the first set of fins have a first fin pitch and the second set of fins have a second fin pitch, the first fin pitch being different than the second fin pitch; and
gates disposed between the first set of fins and a second set of fins, the gates having a width between the first set of fins that is equal to a width of the gates between the second set of fins, wherein gates adjacent to the dielectric pillar directly contact the dielectric pillar.