US 12,255,203 B2
Monolithic three dimensional integrated circuit
Kam-Tou Sio, Zhubei (TW); Jiann-Tyng Tzeng, Hsinchu (TW); and Shih-Wei Peng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 30, 2021, as Appl. No. 17/245,757.
Prior Publication US 2022/0352148 A1, Nov. 3, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 21/822 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 27/0688 (2013.01) [H01L 21/8221 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A monolithic three-dimensional integrated circuit comprising: a single die comprising eight metal layers disposed in a vertical direction, wherein the single die further comprises:
a first cell layer formed below a zeroth metal layer of the eight metal layers of the single die, the first cell layer comprising a first cell having a first active component of the monolithic three-dimensional integrated circuit;
a second cell layer formed in between a third metal layer and a fourth metal layer of the eight metal layers of the single die, the second cell layer comprising a second cell having a second active component, wherein the second cell layer is formed vertically above the first cell layer, wherein
the second cell layer and the first cell layer have identical horizontal dimensions, and wherein
both the first cell layer having the first active component and the second cell layer having the second active component are formed in the single die comprising the eight metal layers disposed in the vertical direction, and
a buried via electrically coupling the first active component of the first cell of the first cell layer with the second active component of the second cell of the second cell layer, wherein
the buried via connects the first cell with the second cell through a third metal layer and a fifth metal layer of the eight metal layers of the single die.