US 12,255,199 B2
Multi-bit structure
Shao-Lun Chien, Hsinchu (TW); Po-Chun Wang, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Chih-Liang Chen, Hsinchu (TW); and Li-Chun Tien, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jan. 17, 2024, as Appl. No. 18/415,211.
Application 18/415,211 is a continuation of application No. 17/876,909, filed on Jul. 29, 2022, granted, now 11,916,058.
Application 17/876,909 is a continuation of application No. 16/915,954, filed on Jun. 29, 2020, granted, now 11,444,071, issued on Sep. 13, 2022.
Prior Publication US 2024/0153942 A1, May 9, 2024
Int. Cl. H01L 27/02 (2006.01); G06F 30/392 (2020.01); H01L 23/522 (2006.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a multi-bit cell having a number M of a plurality of bit cells disposed in a plurality of cell rows having different cell height, M being a positive integer,
wherein a first bit cell and an (M/2)-th bit cell of the plurality of bit cells are arranged in a first column, and the (M/2)-th bit cell and an M-th bit cell of the plurality of bit cells are arranged in a last cell row of the plurality of cell rows.