US 12,255,197 B2
Package-on-package type semiconductor package
Dong Jin Kim, Gwangju (KR); Jin Han Kim, Namyangju-si (KR); Se Woong Cha, Gwangju-si (KR); Ji Hun Lee, Gwangju-si (KR); Joon Dong Kim, Gwangju (KR); and Yeong Beom Ko, Gwangju (KR)
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed on Nov. 18, 2022, as Appl. No. 17/989,791.
Application 17/989,791 is a continuation of application No. 17/120,991, filed on Dec. 14, 2020, granted, now 11,508,712.
Application 17/120,991 is a continuation of application No. 16/412,166, filed on May 14, 2019, granted, now 10,867,984, issued on Dec. 15, 2020.
Application 16/412,166 is a continuation of application No. 15/683,065, filed on Aug. 22, 2017, granted, now 10,290,621, issued on May 14, 2019.
Application 15/683,065 is a continuation of application No. 14/828,984, filed on Aug. 18, 2015, granted, now 9,741,701, issued on Aug. 22, 2017.
Claims priority of application No. 10-2014-0107512 (KR), filed on Aug. 19, 2014.
Prior Publication US 2023/0187432 A1, Jun. 15, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 21/48 (2006.01)
CPC H01L 25/50 (2013.01) [H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 25/105 (2013.01); H01L 21/486 (2013.01); H01L 21/568 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
an upper substrate comprising an upper substrate top side, an upper substrate bottom side, and an upper substrate lateral side between the upper substrate top side and the upper substrate bottom side;
a lower substrate comprising a lower substrate top side, a lower substrate bottom side, and a lower substrate lateral side between the lower substrate top side and the lower substrate bottom side;
a semiconductor die comprising a die top side, a die bottom side, and a die lateral side between the die top side and the die bottom side, wherein the die bottom side is coupled to the lower substrate top side;
conductive pillars peripherally around the semiconductor die, wherein each conductive pillar comprises a conductive pillar top side coupled to the upper substrate bottom side and a conductive pillar bottom side coupled to the lower substrate top side, and wherein at least one of the conductive pillar top side and the conductive pillar bottom side of each conductive pillar is respectively coupled to the upper substrate bottom side and the lower substrate top side via an attachment material comprising solder or conductive adhesive; and
an encapsulating material between the upper substrate bottom side and the lower substrate top side, wherein the encapsulating material encapsulates the die lateral side and each conductive pillar lateral side; and
wherein one of the lower substrate and the upper substrate is a printed circuit board.