US 12,255,196 B2
Semiconductor package with thermal relaxation block and manufacturing method thereof
Shih-Wei Chen, Hsinchu (TW); Chih-Hua Chen, Hsinchu County (TW); Hsin-Yu Pan, Taipei (TW); Hao-Yi Tsai, Hsinchu (TW); Lipu Kris Chuang, Hsinchu (TW); and Tin-Hao Kuo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/361,921.
Application 16/898,409 is a division of application No. 16/103,938, filed on Aug. 15, 2018, granted, now 10,720,416, issued on Jul. 21, 2020.
Application 18/361,921 is a continuation of application No. 17/721,342, filed on Apr. 14, 2022, granted, now 11,830,866.
Application 17/721,342 is a continuation of application No. 16/898,409, filed on Jun. 10, 2020, granted, now 11,309,302, issued on Apr. 19, 2022.
Prior Publication US 2023/0378151 A1, Nov. 23, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/34 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/33 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/023 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73257 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a bottom package having a redistribution structure and a semiconductor die electrically connected to the redistribution structure;
a top package disposed on the redistribution structure of the bottom package, wherein the redistribution structure is disposed between the top package and the semiconductor die of the bottom package, and the top package is spaced apart from the semiconductor die of the bottom package by the redistribution structure;
an underfill disposed between the top package and the bottom package; and
a heat dissipating structure disposed over the bottom package,
wherein the heat dissipating structure includes a thermal relaxation block disposed beside the top package, the redistribution structure includes a ground plane, and the thermal relaxation block is electrically connected to the ground plane of the redistribution structure.