US 12,255,189 B2
Secure semiconductor integration and method for making thereof
Farhang Yazdani, Santa Clara, CA (US)
Assigned to BroadPak Corporation, San Jose, CA (US)
Filed by BroadPak Corporation, San Jose, CA (US)
Filed on Apr. 14, 2021, as Appl. No. 17/229,866.
Application 17/229,866 is a continuation of application No. 17/196,721, filed on Mar. 9, 2021, granted, now 11,569,208.
Prior Publication US 2022/0293575 A1, Sep. 15, 2022
Int. Cl. H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 23/00 (2006.01); H01L 23/04 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/31 (2006.01); H01L 23/36 (2006.01); H01L 23/467 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 25/105 (2013.01) [H01L 21/486 (2013.01); H01L 21/52 (2013.01); H01L 23/04 (2013.01); H01L 23/13 (2013.01); H01L 23/147 (2013.01); H01L 23/3107 (2013.01); H01L 23/36 (2013.01); H01L 23/467 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/573 (2013.01); H01L 23/66 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 23/5383 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1082 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/30107 (2013.01); Y10T 29/53174 (2015.01); Y10T 29/53178 (2015.01); Y10T 29/53183 (2015.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit package comprising:
a non-cavity, fully planar heat spreader, wherein
the non-cavity, fully planar heat spreader having no protrusions,
said non-cavity, fully planar heat spreader including at least a first non-cavity, fully planar heat spreader surface and a second non-cavity, fully planar heat spreader surface;
one or more substrate(s), wherein
said one or more substrate(s) including at least a first substrate surface and a second substrate surface;
one or more standoff(s) substrate(s), wherein
said standoff substrate is a passive substrate; and
one or more component(s), wherein
said one or more component(s) is/are directly mounted and attached on said first substrate surface of said one or more substrate(s),
said second substrate surface of said one or more substrate(s) is/are directly mounted and attached on said first non-cavity, fully planar heat spreader surface of said non-cavity, fully planar heat spreader,
said one or more standoff(s) substrate(s) is/are directly mounted and attached on said first non-cavity, fully planar heat spreader surface of said non-cavity, fully planar heat spreader forming one or more cavity(ies)/clearance(s), and
said one or more component(s) and said one or more substrate(s) are located inside said one or more cavity(ies)/clearance(s).