| CPC H01L 25/0657 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 20 Claims |

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1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a semiconductor layer;
forming a memory stack on the semiconductor layer;
forming a channel structure extending through the memory stack and the semiconductor layer;
exposing an end of the channel structure abutting the semiconductor layer; and
replacing a portion of the channel structure abutting the semiconductor layer with a semiconductor plug.
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